Non-volatile memory devices are employed in a wide variety of electrical devices, such as cameras or cell phones in standalone applications and Chipcard or automotive controllers in embedded applications. One type of non-volatile memory device is an electrically erasable and programmable read-only memory (EEPROM) which employs an array of flash cells. A conventional flash cell, sometimes called a floating gate transistor memory cell, is similar to a field effect transistor, having a channel region between a source and a drain in a substrate and a control gate over the channel region. In addition, the flash cell has a floating gate between the control gate and the channel region which is separated from the channel region by a layer of gate oxide and from the control gate by an inter-poly dielectric layer so as to be electrically isolated or “floating.” The array of flash cells are arranged in a grid of word lines and bit lines, with the control gate of each flash cell being connected to a word line and the drain being connected to a bit line.
According to some techniques, a flash cell is written to or programmed by applying a positive programming voltage to the control gate and a negative programming voltage to the drain, source, and body of the device so that a sufficiently large field develops across the tunnel oxide to induce Fowler-Nordheim tunneling. The voltage applied to the control gate capacitively couples to the floating gate and therefore determines the field across the tunnel oxide and therewith the amount of negative charge residing or retained on the floating gate after programming. The amount of charge, in-turn, determines the minimum voltage, or threshold voltage, that must be applied to the control gate during a reading operation to turn “on” the flash cell and conduct current between the source and drain. As the negative charge on a floating gate increases, the threshold voltage of the cell correspondingly increases.
Accordingly, the amount of charge stored on the floating gate during writing and erasing is used to set a memory or logic state of the flash cell. Note that, according to the present disclosure, the terms “writing” and “erasing” are each defined or considered to be “programming” of the flash cell. For example, a flash cell erased or programmed with a relatively low charge will have a threshold voltage at the low end of the threshold window and may represent a logic “1”, while a flash cell written to or programmed with a relatively high charge will have a threshold voltage at the high end of the threshold window and may represent a logic “0”, or vice-versa. In some EEPROM memories, the amount of charge can be programmed so as to represent more than two logic states. For example, in principle, each distinct threshold voltage level within the threshold window may be used to designate a definite memory state of the flash cell.
To read a flash cell, according to one technique, an operating or read voltage is applied to the control gate while grounding the source and the substrate. The level of current flowing between the source and the drain is sensed and converted to a voltage which is compared to one or more reference voltages in a sense amplifier to determine the programmed state of the flash cell for the given read voltage. The magnitude of current drawn by a flash cell being read depends on the amount of charge stored in the floating gate.
Typically, the read voltage is at a level near the midpoint of the threshold window. If the threshold voltage of the cell is less than the read voltage, the flash cell will turn “on” and conduct current, with the current being greater the further the threshold voltage is below the read voltage. Conversely, if the threshold voltage is greater than the read voltage, the flash cell will remain “off”. In order to guarantee reliability, there must be a gap or separation between the threshold voltages associated with the logic states so that the logic states of the cells can be reliably determined. For example, if a read voltage of 3 volts is employed, it may be preferred that a flash cell desired to be at a logic state of “1” have a threshold voltage less than 2 volts and a flash cell desired to be at a logic state of “0” of greater than 4 volts. Separating the threshold voltages associated with the logic states ensures adequate read current as well as improves the reliability of sensing.
In conventional flash memory devices, data is stored by first programming the flash cells to low threshold voltage (i.e. erasing) and then programming the flash cells to a target threshold voltage representative of the data (i.e. writing). According to one technique, a flash cell is erased or programmed to a low threshold voltage by applying an erase pulse having a negative voltage magnitude for a defined time to the control gate while the drain, source, and body of the transistor are held at a positive voltage. As a result, electrons in the floating gate are induced to pass through the gate oxide to the body by Fowler-Nordheim (FN) tunneling such that the charge in the floating gate is reduced, thereby reducing the threshold voltage of the flash cell. Other erase techniques can also be employed.
Typically, blocks of cells are erased simultaneously, such as a complete row or a group of rows in an array, for example. After such a block erase, not all cells of the block will have exactly the same threshold voltage, but will have a normal distribution of threshold voltages due to the variations between cells.
One problem associated with EEPROMs is that after repeated programming cycles (i.e. writing and erasing), there is a change in the programming behavior of the cells (i.e. the write behavior and the erase behavior). This change is normally caused by an accumulation of trapped charges in proximity to the floating gate which can affect either the reading of the cell and/or the electron tunneling characteristics during writing and erasing. Such effects are sometimes referred to as endurance or cycling degradation. Over time, the accumulation of trapped charges from such cycling changes the threshold voltage distribution of the blocks of cells when in the erased state. Generally, cycling degradation causes an increase in the threshold voltages over time following a given erase scheme which, as a result, narrows the threshold window by raising the low end of the threshold window. Eventually, the erased threshold voltage of some cells may be increased to a level that causes errors in reading the proper state of the cell with the given erase scheme and, ultimately, limits the allowable number of cycles of the memory.
Several techniques have been developed to address this issue, each of which fits into one of two general categories. The first category includes those techniques that require a counter which holds a cycle count for a defined portion of the memory. According to one such technique, by recording the cycle count, the read level can be adjusted at one or more predetermined cycle counts based on known cycling degradation characteristics of the memory and thereby maintain the window for a larger number of cycles. Alternatively, the program bias conditions (i.e. the writing and erasing bias conditions) can be changed as a function of cycle count based on the known cycling degradation characteristics of the memory.
The second category includes those techniques that employ some form of iterative pulsing, sometimes referred to as distribution shaping, which are typically characterized by many iterations of programming (write/erase) and verify (read) steps. One such approach is an incremental step pulse programming (or erase) scheme, where the programming (or erase) voltage is applied to the cell in steps of increasing magnitude. A verify (read) is done after each step (pulse) to determine if a predetermined number of memory cells have reached a target threshold voltage level, at which point the pulsing is stopped. Another approach involves iterating between writing and erasing and individually selecting bits in order to reduce the variation of threshold voltages among a large number of cells. There are many variations of this approach, but all iterate between programming and erasing.
While such techniques are generally successful at improving the performance and extending the life of the memory devices, each has its drawbacks. For example, those techniques employing a counter require that the count be stored, which requires extra system complexity and space for storing and reading out the information. Pulsing techniques require a large amount of time to iterate between the erasing and/or writing and verifying the cell threshold level. Additionally, variable pulses can result in a program and erase throughput which is dependent on cycle count. Often times, anywhere from ten to twenty steps are required to achieve a desired cell distribution.
For these and other reasons, there is a need for the embodiments of the present disclosure.